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1 <!doctype html>
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2
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3 <title>CodeMirror: Verilog/SystemVerilog mode</title>
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4 <meta charset="utf-8"/>
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5 <link rel=stylesheet href="../../doc/docs.css">
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6
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7 <link rel="stylesheet" href="../../lib/codemirror.css">
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8 <script src="../../lib/codemirror.js"></script>
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9 <script src="../../addon/edit/matchbrackets.js"></script>
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10 <script src="verilog.js"></script>
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11 <style>.CodeMirror {border-top: 1px solid black; border-bottom: 1px solid black;}</style>
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12 <div id=nav>
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13 <a href="https://codemirror.net/5"><h1>CodeMirror</h1><img id=logo src="../../doc/logo.png" alt=""></a>
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14
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15 <ul>
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16 <li><a href="../../index.html">Home</a>
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17 <li><a href="../../doc/manual.html">Manual</a>
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18 <li><a href="https://github.com/codemirror/codemirror5">Code</a>
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19 </ul>
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20 <ul>
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21 <li><a href="../index.html">Language modes</a>
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22 <li><a class=active href="#">Verilog/SystemVerilog</a>
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23 </ul>
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24 </div>
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25
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26 <article>
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27 <h2>SystemVerilog mode</h2>
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28
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29 <div><textarea id="code" name="code">
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30 // Literals
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31 1'b0
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32 1'bx
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33 1'bz
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34 16'hDC78
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35 'hdeadbeef
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36 'b0011xxzz
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37 1234
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38 32'd5678
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39 3.4e6
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40 -128.7
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41
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42 // Macro definition
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43 `define BUS_WIDTH = 8;
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44
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45 // Module definition
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46 module block(
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47 input clk,
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48 input rst_n,
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49 input [`BUS_WIDTH-1:0] data_in,
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50 output [`BUS_WIDTH-1:0] data_out
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51 );
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52
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53 always @(posedge clk or negedge rst_n) begin
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54
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55 if (~rst_n) begin
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56 data_out <= 8'b0;
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57 end else begin
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58 data_out <= data_in;
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59 end
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60
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61 if (~rst_n)
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62 data_out <= 8'b0;
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63 else
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64 data_out <= data_in;
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65
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66 if (~rst_n)
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67 begin
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68 data_out <= 8'b0;
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69 end
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70 else
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71 begin
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72 data_out <= data_in;
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73 end
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74
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75 end
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76
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77 endmodule
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78
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79 // Class definition
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80 class test;
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81
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82 /**
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83 * Sum two integers
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84 */
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85 function int sum(int a, int b);
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86 int result = a + b;
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87 string msg = $sformatf("%d + %d = %d", a, b, result);
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88 $display(msg);
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89 return result;
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90 endfunction
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91
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92 task delay(int num_cycles);
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93 repeat(num_cycles) #1;
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94 endtask
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95
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96 endclass
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97
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98 </textarea></div>
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99
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100 <script>
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101 var editor = CodeMirror.fromTextArea(document.getElementById("code"), {
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102 lineNumbers: true,
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103 matchBrackets: true,
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104 mode: {
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105 name: "verilog",
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106 noIndentKeywords: ["package"]
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107 }
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108 });
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109 </script>
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110
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111 <p>
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112 Syntax highlighting and indentation for the Verilog and SystemVerilog languages (IEEE 1800).
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113 <h2>Configuration options:</h2>
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114 <ul>
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115 <li><strong>noIndentKeywords</strong> - List of keywords which should not cause indentation to increase. E.g. ["package", "module"]. Default: None</li>
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116 </ul>
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117 </p>
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118
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119 <p><strong>MIME types defined:</strong> <code>text/x-verilog</code> and <code>text/x-systemverilog</code>.</p>
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120 </article>
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